A continuing design objective in computer technology is to increase the rate of operand processing. A general technique for increasing operand processing is the use of multiple arithmetic logic units (ALU) operating in parallel. Parallel operation may be particularly suitable in applications which utilize data vectors. Such vectors comprise a plurality of elements which are subject to the same functional processing. Although parallel processing of vector elements is an appealing concept, there are many problems encountered in attempting to implement the concept in a computer. Functional processing units typically operate upon data elements which are stored in a main memory and transferred through input/output devices. There can be considerable difficulty encountered in synchronizing the operation of a plurality of ALUs and coordinating the ALU operation with the input and output of data elements. It is difficult to fully utilize a group of parallel logic units to achieve the full capability of all of the units.
In using parallel processing units, a system is typically subject to a catastrophic failure if there is a failure of any one of the processing units.
Examples of parallel processing are shown in U.S. Pat. No. 4,128,880 to Cray, Jr. and in the book Parallelism in Hardware and Software: Real and Apparent Concurrency, Harold Lorin, Prentice-Hall, Inc., copyright 1972.
In view of the potential value of parallel processing to achieve increased operand processing rates, there exists a need for a method and apparatus to optimally control the input and output of operands to parallel processing units, to allocate the logic units for maximum utilization while eliminating the difficulties of synchronization with other computer units as well as synchronization between the parallel processing units. There is further a need to eliminate the possibility of a system failure as a result of a failure of only one of a plurality of parallel processing units.